Misc Publications by Michael B. Taylor

How to build scalable on-chip ILP networks for a decentralized architecture,
by Michael Taylor, Walter Lee, Matt Frank, Saman Amarasinghe, and Anant Agarwal.
MIT/CSAIL Technical Memo MIT-CSAIL-TM-628. Submitted to ASPLOS-2000, April 2000. (pdf)

Design Decisions in the Implementation of a Raw Architecture Workstation,
by Michael B Taylor.
MS Thesis, Cambridge, MA, September, 1999. (pdf)

Baring it all to Software: The Raw Machine,
by Elliot Waingold, Michael Taylor, Vivek Sarkar, Walter Lee, Victor Lee, Jang Kim, Matthew Frank, Peter Finch, Srikrishna Devabhaktuni, Rajeev Barua, Jonathan Babb, Saman Amarasinghe, and Anant Agarwal.
MIT/LCS Technical Report TR-709, March 1997.  (pdf)
 
MRI On the Fly: Accelerating MRI Imaging Using LDA Classification with LDB Feature Extraction,
Y. Joy Ko, Michael B. Taylor
Dartmouth College Computer Science Technical Report PCS-TR96-290, June 1996.
 
DartCVL: The Dartmouth C Vector Library,
Thomas H. Cormen, Sumit Chawla, Preston Crow, Melissa Hirschl, Roberto Hoyle, Keith D. Kotay, Rolf H. Nelson, Nils Nieuwejaar, Scott M. Silver, Michael B. Taylor, and Rajiv Wickremesinghe.
Dartmouth College Computer Science Technical Report PCS-TR95-250, January 1995.
 
Transparent Distributed Java,
by Douglas Decouto, Brad Porter, and Michael Taylor.
6.853 project - modifying Kaffe to transparently distribute threads across a number of machines.
This included a cached, distributed object store. (pdf)
 

Workshops & Talks

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Scalar Operand Networks for Tiled Microprocessors,
2006 Workshop on On- and Off-Chip Interconnection Networks for Multicore Systems (OCIN) (google video)
Stanford, CA. December 2006.

Prototyping Raw,
International Symposium on Computer Architecture, Workshop on Architectural Research Prototyping (WARP)
Boston, MA. June 2006.

Evaluating the Raw Microprocessor: Scalability and Versatility,
International Symposium on Computer Architecture.
Munich, Germany. June 21, 2004.

Evaluating the Raw Microprocessor,
Boston Area Computer Architecture Workshop.
Boston, MA. January 30, 2004.

Scalar Operand Networks,
International Symposium on High Performance Computer Architecture.
Anaheim, California. February 12, 2003.

A 16-issue multiple-program-counter microprocessor with point-to-point scalar operand network,
IEEE International Solid-State Circuits Conference.
San Francisco, California. February 11, 2003. (pdf)   (powerpoint with some transcript)

Panel Chair,
2nd MIT Computer Architecture Workshop,
Gloucester, Massachusetts. September 9, 2002.

The Raw Microprocessor - Exposing Chip Resources to Software,
Symposium on Hardware/Software Interfacing for Performance Enhancements.
St Cloud, Minnesota. April 26, 2002.

The Raw Processor - A Scalable 32-bit Fabric for Embedded and General Purpose Computing,
Hotchips XIII.
Palo Alto, California. August 21, 2001. (pdf , powerpoint with transcript)