Monday, March 26, 2007
Arsenal
 
 An ARSENAL microprocessor challenges our ability to specify, debug, construct, test, describe and program the system. To achieve these types of systems, we need to be able to specify families of related processors and special purpose hardware engines along clean boundaries (such as issue width, pipeline structure, bit width, working set ...) in order to manage the complexity of the system. This is the key difference between an ARSENAL processor and today's system-on-a-chip. Since Computer Vision is a highly heterogeneous application domain, the San Diego Stingray will be designed as an instance of an ARSENAL processor and includes a T2 as one of its components.
 
The Arsenal work is a joint collaboration with UCSD Prof. Steven Swanson.
 
 
The ARSENAL system is targeted towards silicon systems that can only have a small portion of the die area active ("the active core") at any one time due to power limitations. In such a system, the benefits of composing the system out of homogeneous components larger than the active core size are limited. Instead, the optimal system is composed out of  many specialized components which collectively provide the highest performance across the system.